1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, such as an SDRAM (Synchronous Dynamic Random Access Memory) or the like, whose internal circuits operate in synchronism with an external clock and whose output circuit outputs an output signal with a predetermined phase difference or relation with respect to the external clock.
2. Description of the Related Art
As the clocks of CPUs in recent computer systems become faster, an attempt is made to increase the access speeds of DRAMs which are used as a main memory device. As such a fast DRAM has been developed a synchronous DRAM (hereinafter simply called SDRAM) whose apparent access time is shortened by allowing internal circuits to operate in pipe-line in synchronism with an externally supplied clock.
This SDRAM receives, for example, a column address signal in synchronism with the external clock and outputs an output signal like data from the output circuit after several clocks. As one example, the SDRAM has such an internal structure that the column associated circuit from the column address buffer to the data output circuit is separated into plural stages of circuits with pipe-line gates provided between those circuits and the opening and closing of the pipe-line gates is controlled by an internal clock which has a predetermined phase difference to the external clock.
There is a demand from the system side for the SDRAM with the pipe-line structure to output an output signal like data at the timing of a predetermined phase difference with respect to an external clock. This demand is intended to make the gray zone of the access hold time of the output data signal to approach zero as close as possible. To meet this demand, the phase of the internal clock in the SDRAM is controlled in such a way that the internal clock has a predetermined phase difference to the external clock. This can permit a data signal to be output at the timing of a predetermined phase difference to the phase of the external clock after several clocks after the column address is input. This operation can allow the system side to receive the output signal of the memory at a quicker timing with respect to an external clock of a short period and to receive the output signal of the memory at a slower timing with respect to an external clock of a longer period.
While the delay characteristics of the internal circuits having a pipe-line structure are almost fixed regardless of the period of the external clock, however, the timing of the internal clock depends on the period of the external clock. When the period of the external clock is extremely long or short, therefore, the timings of the outputs from the internal circuits are unbalanced with the timing of the internal clock which controls the opening and closing of the pipe-line gates. In this case, the operational margin of the internal circuits may not be secured.